PRODUCT INFORMATION
Product Overview
The General Electric DS200UCPBG5AFB is a Mark V IO Engine CPU Board. This circuit board features an onboard microprocessor and multiple PROM modules. It includes random access memory for processor execution during normal system operation. A dual in-line memory module socket provides primary system memory capacity. The assembly also incorporates a seven-switch configuration block for hardware addressing.
The board interfaces with peripheral systems through dedicated STCA connectors. It supports ARCNET COREBUS communication alongside a COM1 terminal interface monitor port. Internal communication uses J1 and J3 STCA bus connectors. A dedicated Power Control Module daughterboard facilitates communication with FMVED motor controller hardware. Hardware jumper JP2 allows technicians to configure the 486 local bus clock speed.
TECHNICAL DATA
Technical Specifications
| Parameter | Specification |
|---|
| PCB Coating Style | Normal Coating |
|---|
TECHNICAL INFORMATION
Features
- Contains one onboard microprocessor with multiple PROM modules.
- Includes one DIMM socket for system memory hardware.
- Features a seven-position switch block for hardware configuration.
- Provides an ARCNET COREBUS connector for STCA board interfacing.
- Includes JP2 hardware jumper for 486 local bus speed configuration.
- Integrates a Power Control Module daughterboard for FMVED motor controller communications.
TECHNICAL INFORMATION
Applications
- General Electric Mark V turbine control systems.
- FMVED motor controller interface applications.
TECHNICAL INFORMATION
Connections / Interfaces
- ARCNET COREBUS STCA board connector
- COM1 terminal interface monitor STCA board connector
- J1 and J3 STCA board bus connectors
- 34-pin interface connector
- IDE and COM2 connectors (unused during standard operation)
- Inter-board attachment connector
TECHNICAL INFORMATION
Installation Guidelines
- Replacement boards ship with an unpopulated DIMM socket.
- Transfer the existing DIMM from the prior board into the replacement assembly.
- Verify JP2 jumper positioning to match required 486 local bus speed settings.
- Jumpers JP1 and JP3 remain factory-reserved and do not require field adjustment.
TECHNICAL INFORMATION
Configuration Guidelines
- Configure the onboard seven-switch block according to Mark V system documentation.
- Set hardware jumper JP2 for local bus clock selection.
TECHNICAL INFORMATION
Lifecycle / Replacement Information
- The DS200UCPBG5AFB replaces matching Mark V IO Engine CPU Board assemblies.
PART VERIFICATION
Before You Order
Industrial automation parts can share similar model names, suffixes and revisions. Confirm the complete manufacturer Part Number before purchase.
01Check Part NumberMatch the complete ordering code on the existing unit.
02Confirm RevisionCheck suffix, hardware or firmware when applicable.
03Send a Label PhotoWe can review a clear label photo when identification is uncertain.
ORDERING PROCESS
From RFQ to Dispatch
1Submit Part Number2Verify Product Identity3Confirm Stock & Condition4Issue Quotation5Dispatch & Tracking
PRODUCT FAQ
Frequently Asked Questions
Does the DS200UCPBG5AFB include a DIMM upon replacement delivery?
No. Replacement units feature an empty DIMM socket, requiring module transfer from the original board.
What is the function of jumper JP2 on the DS200UCPBG5AFB board?
Jumper JP2 configures the 486 local bus speed setting on the CPU board.
Which daughterboard is installed on the DS200UCPBG5AFB?
The board incorporates a Power Control Module daughterboard for communication with FMVED motor controllers.
What is the purpose of the IDE and COM2 connectors?
These connectors remain unused during normal Mark V control operations.
